When electrons start slipping through walls, it’s not science fiction—it’s quantum tunneling, and it’s the invisible barrier standing between today’s fastest chips and the next leap in computing power. At KAIST, Professor Yong-Hoon Kim and his team have peered into this atomic-scale frontier, using quantum simulations to predict the ultimate limit of how small transistors can get: 1.3 nanometers. That’s less than five atoms wide.
For decades, the semiconductor industry has relied on shrinking transistors to boost performance and efficiency, packing more power into every square millimeter of silicon. But as chips enter the so-called 2-nanometer era, the physical size of transistors still hovers above 10 nm. The real challenge isn’t just miniaturization—it’s control. At atomic scales, electrons defy classical physics, tunneling through barriers and leaking current even when switches are meant to be off. This quantum effect has long been a theoretical speed bump, but now, for the first time, researchers have quantified its hard limit.
The KAIST team’s breakthrough lies in their use of ab initio, or first-principles, calculations—simulations grounded purely in quantum mechanics, with no reliance on experimental data. Building on their own multi-space constrained-search density functional theory (MS-DFT) framework, they simulated the behavior of electrons at the critical interface between metal electrodes and a two-dimensional semiconductor channel made of monolayer molybdenum disulfide (MoS₂). This is where current enters the transistor, and where atomic-level imperfections can derail performance.
Using computational versions of the transfer length method (TLM)—a gold-standard experimental technique—they mapped how deeply electrons penetrate the semiconductor depending on the metal’s work function and the atomic geometry of the contact. What they found reshapes the conversation: the quantum tunneling limit isn’t fixed. It’s tunable. By optimizing the metal and interface design, they showed that electron leakage can be contained at lengths below 4 nm, with the ultimate scaling limit reaching 1.3 nm. This means future transistors could be more than twice as small as today’s cutting-edge designs.
The implications are profound. Chipmakers can now simulate and predict device performance before fabricating a single prototype, saving time and resources. Materials and contact structures can be screened virtually, accelerating the path to next-generation electronics for AI, mobile computing, and beyond. As the industry approaches the end of silicon’s reign, this work opens a new chapter—one written not in fabrication labs, but in the language of quantum physics and simulation.
The transistor isn’t dead. It’s just getting smaller than ever thought possible.