The AI That Designs Its Own Circuits

The Circuit Whisperers: How AI Learned to Design Electronics From Scratch

In a University of Utah laboratory, something unusual happened. A cluster of large language models, working together like a committee of experienced engineers, designed a working operational amplifier from scratch—then produced three alternative versions that no textbook had ever described. One of those novel designs outperformed all the conventional options by a factor of three. It did this in roughly ninety seconds. A human engineer, working through the same problem with traditional methods, would typically need anywhere from several days to several weeks.

That acceleration—forty times faster than current state-of-the-art approaches—is the headline number from a new paper in analog circuit design automation. But the more profound contribution isn't speed. It's scope. The system, called AaLLM (Analog-augmented Large Language Model), doesn't just size components within a pre-drawn circuit. It generates the circuit topology—the fundamental arrangement of transistors, capacitors, and resistors—from scratch, then sizes every component to meet exact specifications. It does this end-to-end, in a single automated pipeline, with a claimed success rate of over 91 percent.

This matters because analog circuit design has long been considered one of the last bastions of irreplaceable human expertise in electronics. Digital circuits can be synthesized automatically; analog can't—or rather, couldn't. The design space is nonlinear and high-dimensional, meaning small changes in one parameter cascade unpredictably through the rest of the system. Traditional optimization algorithms churn through thousands of simulations to find workable component values. Human engineers bring intuition: a sense of which topology will work for a given set of requirements, an instinct for where to start, an ability to diagnose why something isn't working and make targeted adjustments.

The authors of AaLLM argue that large language models can now replicate these capabilities—and exceed them. Their system doesn't just find component values; it invents circuit structures. It doesn't just meet specifications; it explains its reasoning, identifies failures, and corrects them systematically. And it does so by grounding itself in the actual physics of circuit behavior, not just pattern-matching against training data.

The implications extend beyond engineering efficiency. Analog circuits are everywhere: they process signals in everything from smartphones to medical implants, from car brake sensors to satellite communications. Better, faster analog design automation could accelerate the development of more sophisticated sensors, lower-power devices, and higher-performance communication systems. It could democratize access to custom chip design, allowing smaller teams and organizations to build specialized electronics without assembling a team of PhD-level analog designers.

The Architecture of Electronic Intuition

To understand what AaLLM does, it helps to understand what analog circuit design actually involves. When an engineer sets out to build an operational amplifier—a fundamental building block of analog electronics—they face two interlocking problems.

The first is topology: what arrangement of components will do the job? A simple two-transistor differential pair? A cascode structure for higher gain? A folded cascade for better bandwidth? Each topology has different strengths and weaknesses, different trade-off profiles. Choosing the wrong topology means the design will struggle to meet specifications no matter how cleverly the components are sized.

The second problem is sizing: once you've chosen a topology, what are the exact values of every component? What should the width and length of each transistor be? What capacitance values will give you the bandwidth you need while maintaining stability? These questions interact in complex ways. Increase the width of a transistor to get more current, and you change the biasing conditions throughout the circuit, which affects gain, which affects bandwidth, which may require adjusting other components, which changes the biasing conditions again...

For decades, the standard approach to sizing has been optimization: start with initial guesses, run a simulation (traditionally using a tool called SPICE, which stands for Simulation Program with Integrated Circuit Emphasis), see how close you are to the target specifications, adjust the parameters, simulate again, repeat. Modern optimization algorithms can do this reasonably well, but it requires thousands of simulations and can still get stuck in local minima—configurations that look good locally but aren't actually optimal. And even the best optimization algorithm can't help if you've started with the wrong topology.

Most previous attempts at AI-assisted circuit design have focused on one half of the problem or the other. Some systems use machine learning to map specifications to component values, but they assume someone has already chosen the topology. Others can generate circuit structures, but then require conventional optimization to size them. Neither approach captures the full workflow of an experienced designer, who thinks about topology and sizing simultaneously, drawing on deep knowledge of how different structures behave.

AaLLM is designed to close this gap. Its architecture consists of three interacting subsystems: a topology generator, a retrieval-augmented knowledge system, and a tri-agent sizing loop. Each serves a distinct function, and their integration is what enables the system to work end-to-end.

The topology generator uses a fine-tuned sequence-to-sequence model—an extension of the FLAN-T5 language model—trained to translate performance specifications into circuit structures. The model represents circuits as bipartite component-node matrices: tables that encode which components connect to which nodes in the circuit. This representation is crucial because it decouples the topological problem (what connects to what) from the sizing problem (what the values are), while still capturing all the information needed to generate a valid circuit.

The training process follows a curriculum: first, the model learns to predict connections given a fixed set of components; then, it learns to predict both components and connections simultaneously. This staged approach lets the model gradually acquire increasingly complex capabilities without being overwhelmed.

The output of the topology generator is not a single circuit but a ranked list of candidates, each evaluated through preliminary SPICE simulation. This gives the downstream selection stage a shortlist of options grounded in actual electrical behavior, not just theoretical potential.

Teaching Machines to Read Circuit Theory

The ranking from the topology generator is informative but not definitive. A circuit that performs well with default component values might perform even better with different sizing, and a circuit that seems mediocre might excel once properly optimized. To make the final selection, AaLLM uses a retrieval-augmented selection module that consults a knowledge base of analog circuit literature.

This is where AaLLM diverges most sharply from pure pattern-matching approaches. Rather than relying solely on what the model learned during training, the system actively retrieves relevant knowledge—textbook explanations, research papers, design guidelines—and uses that knowledge to inform its decisions. The retrieval system uses two complementary search methods in parallel.

The first is semantic search: the system encodes chunks of text as vectors and finds chunks whose vectors are close to the query vector. This captures conceptual relationships—if you ask about improving common-mode rejection, the system might retrieve discussions of bias current matching, even if that exact phrase wasn't in your query.

The second is keyword search using BM25, a classical information retrieval algorithm that scores documents based on exact term matches. This handles technical acronyms and precise terminology that semantic search sometimes confuses. A query about CMRR (common-mode rejection ratio) won't accidentally retrieve articles about PSRR (power-supply rejection ratio), even though the concepts are related.

The results from both searches are combined using weighted reciprocal rank fusion, a technique that gives high scores to documents that rank well on both methods. The combined retrieval results are then passed to a selection agent that chooses the most appropriate topology for the given specifications, with explanations grounded in the retrieved knowledge.

A distinctive feature of this knowledge base is contextual augmentation. Before embedding text for semantic search, the system passes each chunk through an LLM that creates a short description situating the chunk within its document. This helps the retrieval system understand why a particular passage is relevant, not just what it contains.

The knowledge base isn't static. The system includes a web-scraping tool that allows it to fetch and incorporate new research papers during operation. The retrieval module autonomously expands its knowledge base, keeping the agents up-to-date with the latest research without requiring manual curation. This dynamic update capability addresses a fundamental limitation of purely training-based approaches: a model trained on data up to a certain date can't know about discoveries made afterward.

This matters because analog circuit design is a field where knowledge accumulates. New topologies and sizing techniques appear in the literature constantly. A system that can incorporate new knowledge on demand has a fundamental advantage over one limited to its training data.

A Committee of Digital Engineers

Once a topology has been selected, the system moves to the sizing phase: determining the exact values of all circuit parameters to meet the target specifications. This is where AaLLM's tri-agent architecture comes into play.

The system employs three specialized agents, each with a distinct role: a Designer, a Critic, and an Evaluator. These roles mirror the workflow of a skilled human design team. The Critic is "the eyes"—it receives the current simulation results and produces a structured diagnosis: how far is each specification from its target? Which ones are on-track, which are minor misses, which are severe failures? Most importantly, which components are most directly responsible for each failure?

The Evaluator is "the brain"—it receives the Critic's diagnosis and decides on a strategy. Should the system focus on meeting one specification at a time, or try to optimize multiple specifications simultaneously? If one spec is severely off-target, should others be allowed to degrade temporarily to bring it into range? The Evaluator's job is to set the agenda for the next iteration.

The Designer is "the hands"—it takes the strategy from the Evaluator and determines specific parameter changes. Based on the diagnosis of what's wrong and the strategy for fixing it, the Designer outputs adjusted component values. These values are then simulated in SPICE, and the loop repeats.

This separation of roles is intentional. A single agent asked to do everything at once would need to switch between diagnostic reasoning, strategic planning, and numerical adjustment. Research in cognitive science suggests that conflating different reasoning modes leads to worse performance on each. By giving each agent a specialized role, AaLLM can optimize each mode independently.

The sizing loop uses a curriculum-based approach: design objectives are addressed in a deliberate sequence, allowing each specification to be met without disrupting previously satisfied ones. This avoids the common problem in optimization where improving one specification causes another to slip. The Evaluator acts as an arbiter, preventing the Designer from "chasing" specifications in circles.

The entire loop is supported by the retrieval system. When the sizing agents need to understand why a particular failure is occurring, they can consult the knowledge base for relevant theory. When they're unsure how to adjust a parameter, the retrieval system can provide guidance from textbooks and papers. This grounding in domain knowledge distinguishes AaLLM's sizing from purely numerical optimization.

The authors tested this tri-agent system across a wide range of specifications for operational amplifiers, spanning various combinations of gain, unity-gain bandwidth, phase margin, and bias current. They report that the system meets target specifications in 91.6 percent of cases.

Computational Efficiency Gains

Label	Value
3x–4.5x	3.75 reduction factor
40x	40 reduction factor

Data from Habib, Hart & Fayazi (2026)

Inventing Circuits That Didn't Exist Before

Perhaps the most striking claim in the paper concerns topology generation. Most AI-assisted circuit design systems work within a fixed library of known topologies—they can select from existing structures but not create new ones. AaLLM, the authors argue, goes further: it generates novel topologies that don't appear in the literature, validates them through simulation and theoretical analysis, and produces designs that can outperform existing approaches.

The key to this capability is the fine-tuned sequence-to-sequence model, trained on circuit-structure pairs. By learning the relationship between desired specifications and circuit architectures across hundreds of examples, the model doesn't just memorize existing topologies—it learns the underlying principles of how circuit structures relate to electrical behavior. This enables generalization: given specifications outside the training distribution, the model can propose structures that combine elements in new ways.

The paper reports that AaLLM-generated novel topologies achieve a figure of merit (FoM) comparable to known topologies, and up to three times higher for certain circuits. The figure of merit combines multiple performance metrics—gain, bandwidth, power consumption, etc.—into a single number for comparison. A three-fold improvement in FoM is substantial; it means the circuit delivers significantly better performance across its key specifications simultaneously.

This capability raises interesting questions about what "novel" means in circuit design. Analog circuits have been engineered for over a century; the basic building blocks—transistors, resistors, capacitors—are well understood, and their combinations have been extensively explored. It's tempting to assume that any useful topology has already been discovered. But the design space is vast—the number of possible ways to connect even a modest number of components is astronomical—and the search has been constrained by human creativity and the practical difficulty of exploring alternatives.

AaLLM doesn't have those constraints. Given a set of specifications, it can search the combinatorial space of connections systematically, evaluating candidates through rapid simulation. The fact that it produces structures not seen in the literature doesn't mean those structures are necessarily better in every way; novelty and performance don't always align. But it does suggest that human designers may not have exhausted the space of useful analog topologies.

Speed Without Sacrifice

Beyond qualitative capabilities, the paper reports striking quantitative improvements in efficiency. Compared to state-of-the-art multi-agent LLM pipelines for circuit sizing, AaLLM achieves a three-to-four-and-a-half times reduction in the number of SPICE simulations required at inference. And compared to existing approaches more broadly, it reports a forty-fold decrease in wall-clock time.

These numbers are significant because SPICE simulations are computationally expensive. A single simulation of a complex analog circuit can take seconds to minutes. A sizing run that requires thousands of simulations can consume hours of compute time. Reducing the number of simulations by a factor of three to four-and-a-half directly translates to faster turnaround for designers.

The forty-fold reduction in wall-clock time compared to existing approaches is more dramatic, but the comparison is less direct—the paper doesn't specify exactly which approaches are included in this comparison or how they were evaluated. It likely includes both optimization-based methods (which require many more simulations) and other LLM-based approaches. But even if the exact figure is approximate, the direction is clear: AaLLM is substantially faster than alternatives.

The efficiency gains come from multiple sources. The topology generator produces a pre-filtered shortlist of candidates, so the sizing loop doesn't need to explore as many possibilities. The curriculum-based sizing approach avoids wastefully chasing specifications in circles. The retrieval system provides relevant knowledge that helps the agents make better decisions faster, rather than blindly exploring parameter space. And the tri-agent architecture's separation of roles reduces the number of iterations needed to diagnose and correct problems.

AaLLM Performance Summary

Label	Value
SPICE Calls	55 %
Wall-clock Time	97.5 %
Success Rate	91.6 %

Data from Habib, Hart & Fayazi (2026)

What It Means for Electronics Development

The implications of faster, more capable analog circuit design automation extend across the electronics industry.

For large semiconductor companies, the appeal is obvious: faster design cycles mean faster time-to-market. Analog blocks are critical components of system-on-chip designs—they're what handle wireless communication, power management, sensor interfacing, and many other functions. Automating the grunt work of analog design could free engineers to focus on higher-level architectural decisions and system integration.

But the bigger story may be democratization. Right now, sophisticated analog design is concentrated in a handful of large companies and research institutions that can afford teams of experienced analog engineers. Startups and smaller companies often must use off-the-shelf analog blocks even when custom designs would serve them better, simply because they lack the expertise to develop alternatives. If AI can make analog design more accessible, it could lower the barrier to innovation in specialized electronics.

This matters for emerging applications. The next generation of medical implants, environmental sensors, and Internet-of-Things devices will require increasingly sophisticated analog circuits—circuits that can detect faint biological signals, operate on microwatts of power, and interface with diverse sensor technologies. Meeting these requirements will require custom analog designs, not one-size-fits-all solutions. AI-assisted design could make such customization economically viable for applications where it currently isn't.

There are also implications for research. Analog circuit research has historically been labor-intensive: developing a new topology or sizing technique requires extensive simulation and often experimental validation. Faster design automation could accelerate the exploration of new circuit concepts, allowing researchers to evaluate more ideas in less time.

Limitations and Open Questions

The paper's results are impressive, but several caveats apply.

First, the 91.6 percent success rate is measured across a specific test bench of specifications. Real-world design problems may include complications—process variations, temperature effects, aging, parasitic elements—that aren't fully captured in the evaluation. The system's performance on industrial-scale design challenges, with all their practical complexities, remains to be demonstrated.

Second, the novel topology generation capability is demonstrated on operational amplifiers and filters. Analog circuits encompass a much broader range of applications: power converters, radio-frequency circuits, data converters, sensor interfaces, and many others. The generalization of AaLLM's topology generation to these other domains isn't proven.

Third, the paper doesn't provide extensive ablation studies showing which components of the system contribute most to its performance. The contribution of retrieval-augmented knowledge, the tri-agent architecture, the curriculum-based sizing, and other elements aren't fully isolated. Understanding which innovations matter most would help guide future research and practical deployment.

Fourth, the novelty of the generated topologies isn't fully quantified. The paper shows that novel topologies can achieve high figure of merit, but doesn't systematically compare the diversity and quality of AaLLM's proposals against alternatives. How does the space of novel topologies compare to what other methods would generate? Are the novel topologies truly distinct from combinations of existing sub-circuits, or are they recombinations of known patterns?

Fifth, the system requires a curated knowledge base to support retrieval. Building and maintaining this knowledge base requires effort, and the quality of retrieval depends on the quality of the source material. For niche applications where the literature is sparse, the retrieval system may have less to work with.

The Path Ahead

Despite these open questions, AaLLM represents a significant step forward in analog circuit design automation. Its end-to-end approach—handling topology generation, selection, and sizing in a unified pipeline—addresses limitations of previous fragmented approaches. Its grounding in domain knowledge through retrieval augmentation provides a principled way to handle unfamiliar specifications. And its tri-agent architecture offers a template for structuring AI systems that need to combine diagnostic, strategic, and executional reasoning.

Several directions for future work suggest themselves.

One is extending the approach to other classes of analog circuits. Operational amplifiers and filters are important, but analog design encompasses much more. Demonstrating that the approach generalizes to RF circuits, data converters, power management, and other domains would strengthen the case for its broader applicability.

Another is tighter integration between topology generation and sizing. Currently, these are somewhat separate stages: the topology generator proposes candidates, the retrieval system selects among them, and the sizing loop optimizes the chosen topology. But topology and sizing interact—the best topology for a given set of specifications may depend on what's achievable with realistic component values. A more tightly coupled approach might explore topology and sizing jointly, potentially finding better solutions than the current staged approach.

A third direction is better evaluation of novel topologies. The paper shows that novel topologies can perform well, but doesn't fully characterize how novel they are or how they relate to existing knowledge. Developing metrics for topology novelty and systematic comparison against human-designed alternatives would clarify the contribution.

A fourth is addressing practical manufacturing constraints. Real integrated circuits are subject to layout effects, process variations, and manufacturing yield considerations that circuit-level simulation doesn't fully capture. Integrating AaLLM with layout tools and yield analysis would move it closer to industrial applicability.

The State of AI in Engineering

AaLLM is part of a broader wave of AI systems applying large language models to engineering problems. The pattern is familiar: instead of training a model to directly map inputs to outputs, researchers prompt a language model to reason about the problem, give it access to tools (simulators, retrieval systems, code execution environments), and structure the reasoning process through multi-agent architectures.

This pattern has shown promise across domains: in software development, in scientific research, in financial analysis. AaLLM demonstrates its applicability to a domain—analog circuit design—that has historically resisted automation due to its reliance on expert intuition and its complex, nonlinear nature.

The key ingredients seem to be: grounding in domain knowledge (through retrieval augmentation, fine-tuning, or both), structured reasoning (through chain-of-thought prompting, multi-agent systems, or other orchestration), and access to accurate simulation (through integration with physical simulators like SPICE). When these elements come together, language models can exhibit capabilities that seem to go beyond pattern matching—diagnostic reasoning, strategic planning, creative synthesis of novel solutions.

Whether these capabilities constitute genuine understanding or sophisticated pattern matching is a question philosophers may debate. For engineers, the pragmatic question is whether the systems work—and AaLLM's reported performance suggests that, by practical measures, they increasingly do.

Novel vs. Known Topology Performance

Label	Value
Known Topologies	1 relative FoM
Novel Topologies	3 relative FoM

Data from Habib, Hart & Fayazi (2026)

A New Tool for Chip Designers

The electronics industry has long relied on automation for digital design while largely manual processes dominate analog work. That asymmetry is a legacy of the different mathematical structures of the two domains: digital circuits have well-defined logic gates and regular structures amenable to synthesis algorithms, while analog circuits have continuous parameter spaces and complex interactions that stymied automation.

The emergence of large language models changes this calculus. Language models can reason about continuous systems, diagnose failures, and generate creative solutions—in domains where pure optimization or pure pattern-matching struggles. AaLLM demonstrates this principle applied to analog circuit design.

The implications take time to unfold. No single paper establishes a new field. But the capabilities demonstrated here—end-to-end automation from specifications to sized netlists, novel topology generation, 40x speed improvements, 91.6 percent success rates—are substantial. They suggest that the era of fully manual analog design may be ending.

What comes next will depend on how these capabilities develop. Can they generalize to broader classes of circuits? Can they be integrated into industrial design flows? Can they be combined with layout and manufacturing tools to produce chips that actually work in silicon? The questions are numerous. But the direction is clear: AI is learning to design electronics, and the learning is accelerating.