Stable Clocks for Flexible Biosensors: How a Grain-of-Salt Circuit Could Transform Wearable Health Technology
The humble wristwatch on your doctor's arm might soon share its precision DNA with the bandage monitoring your heart rate, the patch tracking your glucose, and the e-tattoo measuring your muscle activity. A team from Karlsruhe Institute of Technology has built the first clock-stabilization circuit specifically designed for flexible electronics—the kind of bendy, stretchy, skin-conformable devices that are reshaping healthcare monitoring. Their design consumes less than a tenth of a milliwatt while matching the timing stability that rigid silicon chips deliver, a combination that has eluded engineers working with the exotic materials these devices require.
The achievement matters because flexible electronics are quietly entering clinical and consumer markets, but they've been operating with a hidden flaw: their internal clocks have been unreliable. Unlike the crystal oscillators inside your phone or laptop, which tick with the constancy of planetary orbits, the timing circuits inside flexible sensors have been prone to drifting by as much as 30% depending on temperature, manufacturing variations, or how much they're bent. This isn't merely a technical inconvenience—it translates directly into measurement errors, shortened battery life, and designs that must waste energy building in safety margins to account for timing uncertainty.
The new circuit, described in a paper posted to arXiv by Paula Carolina Lozano Duarte, Georgios Zervakis, and Mehdi Tahoori, takes a different approach. Rather than trying to build a high-precision frequency synthesizer—the kind of sophisticated clock circuits that power our wireless communications—the team designed what they call a "temporal stabilizer": a feedback system that monitors a free-running oscillator and gently nudges it back on track whenever it begins to drift. The architecture achieves 1,000 parts per million long-term frequency accuracy (meaning the clock stays within 0.1% of its target over hours or days) and produces timing jitter of just 2.24 nanoseconds—the minute, rapid fluctuations in when each clock pulse arrives. For biosensors and readout circuits operating at kilohertz frequencies, this stability is precisely what enables accurate analog-to-digital conversion and reliable data communication.
The numbers that tell this story are the efficiency gains. Compared to existing flexible-electronics clocking approaches, the new design reduces power consumption by more than 400 times. Its footprint shrinks by a factor exceeding 15,000 relative to prior flexible voltage-controlled oscillators, and by more than 390 times compared to ring-oscillator solutions. At its largest—supporting the slowest, 1 kilohertz clock—these circuits occupy just 0.0233 square millimeters, an area smaller than a grain of salt. Consuming between 115 and 153 microwatts across all operating modes, the design draws so little power that it can comfortably share a battery with the sensor front-end it clocks, rather than dominating the energy budget as clock circuits have historically done.
The Science
To understand why this work is novel, you need to understand what flexible electronics are made of—and why they're so challenging to build.
Conventional electronics sit on rigid silicon wafers, sliced thin from single-crystal ingots grown in pristine fabs. Silicon transistors achieve their remarkable performance because electrons move through them with relative ease, and because we can build both "n-type" transistors (which conduct using negatively charged electrons) and "p-type" transistors (which conduct using positively charged "holes"). Having both types lets circuit designers create efficient logic gates and analog circuits that consume minimal power while switching rapidly.
Flexible electronics take a different path. They deposit semiconductor materials—often in amorphous or polycrystalline forms—directly onto bendable substrates like plastic films or even paper. The material used in this work, amorphous indium-gallium-zinc oxide (a-IGZO), is a transparent semiconductor that can be applied at low temperatures, making it compatible with cheap plastic substrates that would melt under the high-temperature processing required for crystalline silicon.
The trade-off is severe: IGZO transistors have carrier mobilities between 5 and 20 square centimeters per volt-second, roughly 100 to 1,000 times lower than modern silicon. More critically, only n-type IGZO devices are readily available; there are no good p-type counterparts in this material system. This limitation forces engineers to build everything from n-type transistors alone, using design tricks that mimic the behavior of complementary circuits—a technique called pseudo-CMOS—but which inevitably consume more power and operate more slowly.
Into this constrained world, the team set out to build something no one had attempted before: a phase-locked loop, or PLL. PLLs are ubiquitous in conventional electronics. They're the circuits that generate clean, stable clock signals in microprocessors, radios, and virtually every digital system. A PLL works by comparing an oscillator's output against a reference signal, detecting any difference in phase or frequency, and using that error signal to adjust the oscillator back toward the target. The feedback loop continuously corrects drift, converting an imperfect oscillator into a precise, reference-anchored clock.
The challenge is that classical PLL architectures assume you have p-type devices available. The phase-frequency detector, which measures the difference between the reference and the oscillator, is typically built from both n-type and p-type transistors in complementary configurations. The charge pump, which converts phase errors into a control voltage, similarly relies on push-pull topologies that are difficult to implement with n-type devices alone. And the loop dynamics—the mathematical relationship between correction speed, stability, and noise suppression—are optimized for high-mobility transistors that switch in nanoseconds, not the microseconds or milliseconds that IGZO circuits require.
The team's solution, shown in their schematic (
), reimagines each building block for the constraints of IGZO. The phase-frequency detector uses dynamic D flip-flops built from pseudo-CMOS logic, sized to tolerate the large frequency spreads—exceeding 30%—that IGZO's process variability can produce. The charge pump implements a zero-quiescent-bias design: eliminating any static current path is essential in a technology where leakage currents are poorly controlled and where every microwatt matters. The low-pass filter that smooths the charge pump's output into a control voltage uses passive components—resistors and capacitors—rather than active circuits that would consume power continuously.
At the heart of the circuit sits a three-stage ring oscillator, the simplest possible voltage-controlled oscillator. A ring oscillator consists of an odd number of inverting stages connected in a loop; the signal oscillates because each inversion followed by propagation delay around the loop creates the necessary phase shift. In this design, each stage uses a resistive pull-up and an n-type transistor pull-down—a pseudo-CMOS configuration that works despite the absence of p-type devices. The load capacitor at each stage () dominates the total capacitance and thus the oscillation period. By adjusting only this one parameter, the designers can shift the clock frequency across three decades—from 1 kHz to 300 kHz—without changing any transistor dimensions or circuit topology.
The loop bandwidth is deliberately kept narrow: approximately one-tenth of the reference frequency. This is unconventional in classical PLL design, where high bandwidth often provides faster locking and better tracking. But in IGZO, narrow bandwidth serves multiple purposes simultaneously. It suppresses the flicker noise that dominates at low frequencies in amorphous semiconductors. It reduces the charge pump's switching activity, saving power. And it provides slow-drift tracking—precisely the behavior needed to compensate for temperature variations and gradual threshold-voltage shifts without reacting to every momentary perturbation.
The reference signal can come from any stable source in the 1–300 kHz range. Standard 32.768 kHz watch crystals—the same components found in billions of wristwatches and real-time clocks—are directly compatible with the lower-frequency variants after simple prescaling. A 32.768 kHz crystal divided down can produce 1 kHz or 10 kHz references; for 300 kHz operation, either a dedicated crystal or phase interpolation from a lower-frequency source suffices.
All simulations were performed using Cadence Spectre with device models from PragmatIC's third-generation FlexIC process design kit. Critically, the researchers completed physical layouts for all four frequency variants (
), then extracted parasitic resistances and capacitances to verify that layout-dependent effects don't degrade the reported performance. This isn't a paper design; it's a post-layout verification that accounts for real-world interconnect and device parasitics.
Testing covered 27 process-voltage-temperature (PVT) combinations: three supply voltages (2.7, 3.0, 3.3 V), three process corners (typical, fast, slow), and three temperatures (0°C, 27°C, 45°C). The temperature range captures the wearable body-contact envelope—skin-surface temperatures typically remain below 45°C—and the supply range reflects ±10% tolerance around the nominal 3 V that flexible battery-powered systems commonly tolerate.
What They Found
The results demonstrate that closed-loop clock stabilization is viable in IGZO technology at power and area budgets that fit within flexible system constraints.
At the most demanding operating point—300 kHz at nominal conditions (3 V supply, typical process corner, 27°C)—the PLL consumes 115.4 microwatts total. Of this, the voltage-controlled oscillator dominates at 110.6 microwatts, carrying the only unavoidable static bias current in the topology. The phase-frequency detector draws just 0.2 microwatts, and the charge pump plus low-pass filter together consume 4.6 microwatts. This distribution reflects a deliberate design choice: by concentrating all static power in the VCO and eliminating quiescent currents elsewhere, the topology minimizes total power consumption while keeping the design simple.
The area for this 300 kHz variant is 0.0115 square millimeters—a footprint smaller than a typical dust mote. Changing the target frequency requires adjusting only the VCO load capacitor, not redesigning transistors or layouts. The 150 kHz variant shares the same die area; only the loop-filter passive values change. The 10 kHz variant grows slightly to 0.0125 square millimeters, and the slowest 1 kHz design reaches 0.0233 square millimeters, still microscopic. Across this entire range, power scales modestly from 115 microwatts to 153 microwatts—a factor of 1.3—despite the frequency changing by a factor of 300.
The timing performance tells the story of closed-loop stabilization's value. RMS period jitter of 2.24 nanoseconds at 300 kHz represents just 0.07% of the output period, confirming that the feedback loop effectively bounds short-term timing uncertainty. Long-term frequency accuracy of 1,000 ppm means the locked output stays within 0.1% of the target over extended periods—not through any temperature compensation or calibration, but through continuous reference anchoring via the PLL feedback.
Clock Power as Percentage of System Power
Power consumption comparison showing clock contribution as percentage of total system power. Prior solutions consume up to 90% of power for clocking alone, while the proposed IGZO PLL contributes less than 8% across all systems. At 10 kHz, the clock previously consumed 20.3 mW (90% of system power); the new PLL draws just 0.151 mW.
| Label | Value |
|---|---|
| 1 kHz [4] | 2.93 mW |
| 10 kHz [25] | 20.3 mW |
| 150 kHz [31] | 1.53 mW |
| 300 kHz [23] | 0.91 mW |
PLL Footprint Across Frequency Variants
Die area comparison showing that the proposed PLL occupies 0.0115-0.0233 mm² depending on frequency. This represents a >15,000x reduction compared to prior flexible VCOs (178 mm²) and >390x compared to ring-oscillator solutions.
| Label | Value |
|---|---|
| 1 kHz | 0.0233 |
| 10 kHz | 0.0125 |
| 150 kHz | 0.0115 |
| 300 kHz | 0.0115 |
The PVT robustness results reveal both capabilities and limitations. At 27°C—nominal room temperature—the PLL locks in 8 of 9 corner combinations. All three supply voltages at typical and fast process corners stay within ±7.5% of the 300 kHz target, well within a ±10% tolerance band that's acceptable for most AMS applications. The single failing corner (2.7 V, slow process, producing 233.9 kHz, or -22%) represents an extreme combination of minimum supply and maximum process spread. The researchers note that at the rated supply voltage of 3.0 V, the PLL locks reliably across all process corners.
At 45°C—the upper bound of wearable body-contact temperatures—all nine corners lock within ±2.4% of target, with a maximum deviation of just +1.3% at typical and fast corners. This thermal behavior reflects a key material property: amorphous IGZO has a positive temperature coefficient of carrier mobility, meaning electrons move faster as temperature rises. This causes the VCO to speed up with temperature, creating a predictable but pronounced temperature dependence that the loop compensates within its capture range at elevated temperatures.
At 0°C, the VCO runs 17–39% below the 300 kHz target across all corners and supplies, placing the operating point entirely outside the loop's capture range. The PLL doesn't lock at this temperature for the 300 kHz variant. This isn't a flaw in the PLL topology; it's a physical limitation imposed by IGZO's temperature coefficient. For the intended deployment in wearable applications—where body contact maintains temperatures above 20°C—this limitation is irrelevant. The design's intended operating envelope is 27–45°C, consistent with skin-surface temperatures.
Power scales monotonically with both supply voltage and temperature, as expected. Across the 27 PVT corners, total power ranges from 84 microwatts at the lowest-power corner (0°C, slow process, 2.7 V) to 218 microwatts at the highest (45°C, fast process, 3.3 V). Even at the upper bound, this remains far below the power consumption of alternative clocking approaches.
Why This Changes Things
The significance becomes clear when you examine how flexible AMS systems have been built to date—and how inefficiently they've treated clocking as an afterthought.
The researchers audited four representative published IGZO systems from the recent literature: a flexible RISC-V processor running at 300 kHz, a configurable processor for 150 kHz operation, a mixed-signal inference engine at 10 kHz, and a near-threshold processor targeting approximately 1 kHz. Each system reported its power consumption, but none accounted for the clock generator. When the researchers integrated state-of-the-art IoT CMOS PLLs into these same systems, the clock alone consumed between 30% and 90% of total system power. For the 10 kHz mixed-signal inference engine, the clock consumed 90% of the energy budget. For the 1 kHz near-threshold processor, it consumed 87%.
This isn't a hypothetical problem. It means that published comparisons of flexible AMS systems have systematically understated their actual power consumption, because they excluded the clock generator. It means that engineers making system-level tradeoffs—choosing between architectural approaches, selecting sensor front-ends, deciding on duty-cycling strategies—have been working with incomplete information. And it means that any real-world deployment of these systems would face an uncomfortable reality: the clock circuit, a component typically considered peripheral, becomes the dominant power consumer.
Free-running ring oscillators avoid this power problem but introduce a different one: unbounded frequency drift. In IGZO, threshold voltages can shift by hundreds of millivolts due to manufacturing variation, temperature changes, bias stress, or mechanical strain. In a ring oscillator, such shifts translate directly into frequency errors. The researchers estimate that moderate threshold-voltage shifts can produce frequency errors exceeding 30%, which degrades ADC sampling accuracy and forces conservative timing guard-bands that waste energy on every clock cycle. There's no mechanism to bound the accumulated phase error over time; the clock simply drifts, and systems must either tolerate the uncertainty or periodically recalibrate at the cost of additional complexity and power.
The proposed PLL addresses both problems simultaneously. Its power consumption—115 to 153 microwatts across all variants—is low enough to fit within flexible system budgets without dominating the power budget. Its closed-loop operation provides bounded frequency accuracy that free-running oscillators cannot achieve. And its reference-anchored stability means that long-term timing accuracy depends on the reference, not on IGZO's notoriously variable transistor parameters.
The efficiency comparison is stark. Prior flexible VCOs achieved area footprints of 178 square millimeters; the new PLL occupies 0.0115 square millimeters, a 15,000-fold reduction. Ring-oscillator solutions that might provide similar frequency ranges consumed on the order of 50 milliwatts; the new PLL draws 0.15 milliwatts, a 300-fold improvement. When compared across the four target systems against a state-of-the-art IoT CMOS PLL, the IGZO PLL's clock contribution ranges from 0.5% to 7.6% of total system power—dramatically better than the 30–90% share that alternative clocking imposes.
![Figure 6: Absolute system power when each target is clocked by a SoA IoT CMOS PLL [14] (left bar) versus the proposed IGZO PLL (right bar). The system power (blue) is identical in both bars; only the clock contribution differs. Percentages above each bar indicate the clock’s share of total power.](https://arxiv.org/html/2607.29357v1/x6.png)
The design philosophy matters here. Rather than targeting high-precision frequency synthesis—the kind of sophistication that enables gigahertz clock synthesis in modern smartphones—the team designed for "temporal stabilization." The goal isn't to generate arbitrary frequencies with parts-per-billion accuracy. It's to take a free-running oscillator that's inherently unstable and use minimal feedback to bound its long-term drift. This reframes the design target from "make the clock more precise" to "make the clock predictable," which turns out to be exactly what flexible AMS systems need.
For biosensors, predictable timing means more accurate sampling. An ADC converting analog sensor signals to digital data needs to sample at consistent intervals; timing jitter and drift introduce errors that look like noise in the measured signal, degrading resolution and requiring oversampling or filtering to compensate. Stable clocks allow ADCs to operate at their designed accuracy without additional margin, enabling lower power consumption (less oversampling needed) or higher quality (same power, better signal).
For digital processing blocks—the microprocessors and inference engines that interpret sensor data—predictable timing means simpler synchronization. Digital circuits communicate across clock domains by using handshaking protocols or dual-ported memories that account for frequency differences. A clock that stays within 1,000 ppm of its target simplifies this significantly compared to a clock that might wander by 30% over temperature. The designers can use smaller buffers, simpler state machines, and less conservative timing margins, all of which translate to area and power savings in the host system.
For system architects designing complete flexible platforms, a low-power PLL means clocking stops being an afterthought that consumes most of the power budget. It becomes a building block that contributes modestly—115 microwatts, less than many sensor front-ends—and provides a service (stable clocking) that enables better performance everywhere else in the system.
What's Next
Several questions remain open, and the path forward involves both characterizing the design in silicon and extending its capabilities.
The most immediate caveat is temperature. The PLL doesn't lock at 0°C for the 300 kHz variant because IGZO's positive temperature coefficient of mobility pushes the VCO below the loop's capture range. For wearable applications, this is unlikely to be a problem: skin-contact devices operate well above room temperature, and the intended deployment envelope is 27–45°C. But for industrial or environmental sensing applications where flexible electronics might be deployed in cold conditions, the current design would need modification—either by rebiasing the VCO, selecting larger load capacitors to shift the lock point, or accepting operation at reduced frequencies.
The reference requirement deserves further study. The PLL needs a reference clock to maintain lock, and while standard 32.768 kHz watch crystals are compatible with the lower-frequency variants, the crystal itself is an external component that must be mounted and connected. For fully integrated flexible systems, the ideal solution would be an on-chip reference—a relaxation oscillator or RC oscillator calibrated once and then maintained by the PLL. The researchers note that their design requires the reference only intermittently, since the narrow loop bandwidth allows the PLL to maintain lock during brief reference interruptions. This is important for duty-cycled systems that periodically sleep to save power, but it doesn't eliminate the need for an external reference entirely.
Long-term reliability is unexplored. IGZO TFTs exhibit bias-stress effects—threshold voltages that shift over time when devices are held in states with sustained electric fields. The loop's narrow bandwidth may help here, since it responds slowly to gradual parameter changes, but this hasn't been characterized. If threshold-voltage drift over months or years of operation shifts the VCO outside the capture range, periodic recalibration or reference updates would be needed.
Mechanical robustness—the ability of the PLL to maintain performance under repeated bending or stretching—hasn't been tested. The post-layout simulations assume the layout is fabricated and operated flat, but flexible electronics derive their value from conforming to curved surfaces. IGZO TFTs have demonstrated reasonable mechanical stability in prior work, but the analog blocks in this PLL (particularly the resistors and capacitors in the loop filter) may have different mechanical sensitivities than digital circuits.
On the capabilities side, extending the frequency range could enable new applications. The current design supports 1 kHz to 300 kHz, which covers the digital processing and mixed-signal inference applications surveyed. But higher-frequency operation—perhaps up to 1 MHz—might enable faster ADCs, higher-bandwidth sensor front-ends, or wireless communication interfaces. This would require faster VCO stages, wider loop bandwidth, and possibly different charge-pump sizing, but the architecture should scale.
Integration with the host system is another frontier. The researchers validate their PLL across four representative IGZO AMS systems, showing that closed-loop clock stabilization can be incorporated with modest overhead. But true system integration—placing the PLL alongside sensors, amplifiers, ADCs, and processors on the same flexible substrate, sharing power rails and routing—remains to be demonstrated. System-level challenges include noise coupling from digital switching into sensitive analog blocks, power supply ripple from the charge pump's switching activity, and substrate coupling between adjacent circuits.
The bigger picture is that this work opens a new design space. Before this paper, no one had demonstrated a PLL in any metal-oxide or organic TFT technology. The existence proof matters: it shows the community that closed-loop clock stabilization is possible in these materials, which will inspire further optimization, variation, and extension. Subsequent work can build on this foundation—exploring different loop architectures, optimizing for specific applications, characterizing long-term reliability, and integrating with real-world flexible systems.
The humble wristwatch's precision, delivered to the bandage on your arm. That's the implication of this work: not that flexible electronics will replace rigid silicon, but that they'll be able to do things rigid silicon can't—conform to your body, disappear into your clothing, monitor your health without intruding on your life—while maintaining the timing reliability that makes electronic systems trustworthy. The clock was the missing piece. Now it's not.