The grain-of-sand amplifier that just broke a 6G power record

A power amplifier the size of a grain of sand just set a record for how much wireless energy it can squeeze from a sliver of silicon — and it's the kind of quiet engineering win that will decide whether the next generation of smartphones, planes, and satellites actually work.

The chip, built by researchers at Chalmers University of Technology in Sweden and Tampere University in Finland, produces 18.8 dBm of saturated output power at 50 gigahertz — a frequency band barely used today but poised to carry the data of the coming decade. That doesn't sound like much on its face. But the numbers that matter for the people who design the systems are these: the amplifier packs 2.6 watts of output power into every square millimeter of its core, the highest power density ever reported for a single-way, two-stage CMOS cascode amplifier. For context, the leading comparable designs in the same process family manage 1.3 to 1.6 W/mm². This one nearly doubles them.

Why should a nonspecialist care about a millimeter-wave amplifier? Because this is the transistor-level plumbing that decides whether the 6G networks, satellite internet constellations, and phased-array radars of the near future can be built at all — and at what cost, and with what battery drain stolen from your phone.

The Science

A power amplifier does exactly what its name says: it takes a weak radio signal and turns it into a strong one, boosting it enough to be transmitted across a distance. Every phone, every Wi-Fi router, every base station has them. The trouble is that making a good PA has always been an exercise in tradeoffs. Push for more output power and your efficiency collapses, which means heat, which means wasted energy, which means shorter battery life)Skip. Push for efficiency and you can't reach far enough. And all of this gets dramatically harder as you move to higher frequencies.

The V-band — roughly 40 to 75 GHz — is where the wireless industry is heading, for two reasons. There's an enormous amount of unused spectrum up there, and those high frequencies are lightly licensed, meaning operators don't have to fight regulatory battles for every hertz. V- and E-band channels can carry vastly more data than the crowded spectrum we use today, with low latency to boot. That's what makes them attractive for high-speed wireless links, including the backhaul connections that stitch cell towers together and the satellite links that will underpin future constellations.

The problem is that CMOS — the dominant, cheap manufacturing technology behind virtually all modern silicon — struggles at these frequencies. Its transistors don't have the breakdown voltage you'd like, so generating high output power has historically demanded clever tricks: stacking multiple transistors to share the voltage, or combining the outputs of many small amplifiers to reach useful power levels)Skip. Both approaches carry penalties. Stacking introduces phase mismatches among the stacked devices and routing losses; combining wastes energy in passive networks that merge the signals.

Enter EDMOS — extended-drain MOS — a new flavor of transistor that GlobalFoundries recently introduced in its 22nm FD-SOI process, marketed as 22FDX+. The "extended drain" is a structural modification that lets a single transistor operate at a higher supply voltage without sacrificing the high-frequency speed that makes CMOS appealing in the first place. Higher voltage means higher output power, directly, without the efficiency-killing penalties of stacking or combining. It's an elegant solution: instead of working around the transistor's voltage limits with ever-more-elaborate architecture, just give the transistor a bigger voltage headroom in the first place.

The Chalmers team — Han Zhou, Torgil Kjellberg, Haojie Chang, and Christian Fager — took this idea and pushed it into territory where EDMOS had barely been tried. Prior work had demonstrated EDMOS transistors at the 5G and 6G FR3 bands (roughly 7–24 GHz), but its use at V-band and above remained largely unexplored. That's a big step up in difficulty: at 50 GHz, the wavelength is six millimeters, and every bit of parasitic capacitance, every length of interconnect, every sliver of metal starts to behave like a radio component in its own right.

Their approach combined three strands of careful engineering. First, they selected and laid out an optimal device core — unit transistors with a 1-micrometer gate finger widthholater, 24-nanometer gate length, and 16 gate fingers, combined into arrays of 16 common-source and 16 common-gate devices for the power stage. Second, they used neutralization capacitors ($C_n=58\mathrm{fF}$) strategically placed to cancel the parasitic feedback that destabilizes differential amplifiers at millimeter-wave frequencies, and compensating inductors ($L_s=8\mathrm{pH}...$ 8 nH per their text) to clean up the AM–PM distortion that would otherwise corrupt the signal. Third, they co-designed the output balun — the transformer that converts the differential signal into a single-ended output — together with the transistor's parasitic capacitance and the pad capacitance, folding all of that into a single matching network that presents the optimal impedance $R_{opt}=50\Omega$, $C_{par}=90\mathrm{fF}$ to the core.

The result is a two-stage, fully differential amplifier built in GlobalFoundries' 22nm FDX+ technology. The driver stage uses a common-source transistor with 128 μm total gate width running on 1.2 V; the power stage uses a cascode (two-transistor) topology with 256 μm total gate width at 2.4 V. The entire active core occupies just 0.028 mm²

.

What They Found

The measured numbers tell the story. At the design frequency of 50 GHz, the prototype delivers a saturated output power of 18.8 dBm, a 1-dB compression point ($P_{1dB}$) of 18.1 dBm, and — critically — a power-added efficiency (PAE) of 21% at that compression point. PAE is the metric that captures how much of the DC power drawn from the supply actually ends up as radio-frequency output, and 21% is strong for a two-stage amplifier at this frequency.

Small-signal measurements confirm a 3-dB bandwidth stretching from 47.1 to 53.8 GHz, with 16.2 dB of small-signal gain at center frequency. That's an 11% fractional bandwidth — a wide, useful window, not a narrow spike. When the amplifier is biased closer to class-AB operation, the small-signal gain climbs to 21 dB, at the cost of a bit of efficiency and AM–AM linearity,Skip. Across the 46-to-54 GHz measurement range, the amplifier keeps its 1-dB compression above 16.5 dBm and its PAE above 17.6%, meaning the performance doesn't collapse as you move away from the design frequency [[chart comparison]].

The headline figure is the 2.6 W/mm² power density, computed as saturated power divided by core area. Against a broader survey of PAs spanning CMOS, SiGe, and GaN technologies from 20 to 100 GHz

, this places the design near the practical ceiling for what a single-way CMOS amplifier can achieve. The only design in the comparison table with a higher raw density, 6.4 W/mm², is a 45-nm SOI stacked amplifier from 2014 — but that design relied on a four-transistor stack at a much lower frequency (47 GHz) and consumed a much larger area to reach comparable absolute power, and its power density figure is based on a much more aggressive area accounting.

Let me put the comparison in concrete terms. This work, at 50 GHz, achieves 18.8 dBm $P_{sat}$ and 21% PAE from a 0.028 mm² core. A 2024 RFIC design in the same 22nm FD-SOI process manages 14.3 dBm at 60 GHz with 1.3 W/mm². A 2024 MWTL paper in the same process reaches 14.6 dBm at 76 GHz with 1.6 W/mm². A 2025 MWTL design using the same 22FDX+ EDMOS at a much lower frequency (12 GHz) hits 23.5 dBm and 38% PAE at 1.5 W/mm² — the higher efficiency there reflects the much lower frequency, where transistors behave far more ideally. Only the gallium-nitride (GaN) part compares on raw power — 31.3 dBm at 62 GHz — but GaN lives on silicon-carbide substrates that are expensive, harder to integrate with digital logic, and far larger (4.5 mm² including pads). The whole point of the CMOS work is that you want this performance in the same cheap, mass-producible silicon that already holds the rest of the radio and the digital processor [[chart:0]].

The efficiency story is worth dwelling on. Power-added efficiency of 21% at the 1-dB compression point means five of every six watts drawn from the supply turn into heat, not signal. That sounds wasteful, and it is — but it's the reality of millimeter-wave amplification, and it's dramatically better than the alternatives at this frequency and power level. In a phased-array system with hundreds or thousands of these amplifiers firing simultaneously — the architecture that makes 5G beamforming and future 6G possible — a few points of PAE translate into enormous differences in system power draw, cooling requirements, and ultimately the size of the battery or solar array you need. This efficiency is what makes dense antenna arrays economically viable.

Why This Changes Things

The significance here isn't any single number — it's what the combination of numbers makes possible. High output power, high efficiency, and high power density in a tiny CMOS footprint is the precise recipe the wireless industry needs for the transition from 5G to 6G.

Consider the phased-array architecture that dominates modern millimeter-wave thinking. Instead of one big antenna and one big power amplifier, you steer a beam electronically using hundreds or thousands of small antenna elements, each driven by its own modest amplifier. This is what gives 5G its beamforming magic, and it's how satellites and aircraft radar steer without mechanical parts. But the economics only work if each individual amplifier is small enough and cheap enough to replicate by the thousands — and efficient enough that running them all doesn't melt the device or drain the battery. Power density, not raw power, is the figure of merit that determines whether a phased array is practical. This chip's 2.6 W/mm² attacks exactly that constraint.

There's a second, subtler implication. The supply voltage of 2.4 V for the power stage, made possible by the EDMOS extended drain, is a structural change rather than a tuning tweak. It means the technology can generate high output power without stacking four transistors and paying the efficiency and complexity penalties that stacked designs incur. The TMTT 2014 design that achieved 6.4 W/mm² needed a four-deep stack and 2.4/4.8 V supplies to get there — an architecture with critical reliability concerns. An EDMOS cascode with just two transistors (the common-source plus common-gate pair) gets comparable density with far less architectural risk. As EDMOS matures — and this is only its first appearance at V-band — that advantage compounds.

The measurement setup, with the chip mounted on a copper plate and probed directly (

), also validates that the design works under realistic conditions, not just in simulation. The close agreement between simulated and measured S-parameters across the band, with only a small discrepancy near the band edges, speaks to how carefully the team modeled the parasitics — the stray capacitances and inductances that dominate at 50 GHz.

What's Next

This is, by the paper's own admission, an early demonstration — a proof that EDMOS can work at V-band, not the final word on what it can do. The measured PAE of 21% at $P_{1dB}$, while strong for a two-stage design, leaves room for improvement. GaN designs at similar frequencies reach efficiencies in the high 30s, and even the single-stage CMOS amplifier at 60 GHz in the comparison table manages more than 20% PAE at its (much lower) compression point. The gap between what CMOS should theoretically deliver and what it currently achieves at V-band is closing, but it isn't closed.

There are also open questions the paper raises implicitly. The 18.8 dBm of saturated output power is a good solid number, but a single antenna element — even at 50 GHz — can't reach very far by itself. The real test of this technology will be in arrays: can designers replicate this core hundreds of times, integrate it with the digital and RF front-end circuitry on the same die, and manage the thermal environment when hundreds of 2.4-V amplifiers fire together? Power density helps, but it also concentrates more heat per square millimeter, and cooling becomes its own engineering problem.

The same research group has been pushing toward Doherty architectures and load-modulation techniques (Zhou and Fager, 2026) that extend the efficiency range beyond the single compression point, and toward AI-driven inverse design (Zhou, Chang, and Widén, 2026) that could automate the kind of painstaking core layout this work did by hand. Pairing EDMOS's higher voltage headroom with efficiency-boosting architectures could be the next leap.

For the world beyond the lab, the trajectory is what matters. When 6G arrives later this decade, it will rely on spectrum in bands like this — 50 GHz and above — where the physics is unforgiving. Every smartphone, every base station, every low-Earth-orbit satellite that talks to a handset will need power amplifiers that are tiny, cheap, efficient, and powerful enough to close the link. This chip, occupying an area smaller than the cross-section of a human hair's width, is a meaningful step toward proving that the workhorse material of the digital age — ordinary CMOS — can carry the load. The next decade of wireless may well be decided by how quietly and efficiently the industry can make these millimeter-wave amplifiers, and on that front, the silicon just got a little more capable.